The present invention is directed to processes for fabricating complementary bipolar and BiCMOS transistors for use in high-voltage applications, and more specifically, to a method for making such devices using a double epitaxial growth step to form the collectors for the two devices. This has the benefit of minimizing the thermal budget used in the fabrication process and reducing the up-diffusion of dopants from the buried layers.
The fabrication of complementary bipolar (CB) transistors on a common substrate is of great interest in the production of high-precision, high-frequency and high-voltage analog circuits. A high-performance PNP transistor in conjunction with a NPN transistor in the signal path permits the design of push-pull circuits for analog applications. High-performance PNP devices can also enhance circuit performance by acting as active loads and as drivers in the outputs stages, thereby reducing the current supply.
It has been a continuing technological challenge to integrate vertical PNP devices into a high performance NPN process without significantly degrading the performance of the NPN devices. This is essential for high performance, low noise and high frequency applications such as operational amplifiers, voltage regulators, phase-locked loop circuits, and D/A converters. Other high-voltage and high-frequency applications which could benefit from such a technology include CRT drivers, instrumentation amplifiers, interface circuits and telecommunication circuits.
The article entitled xe2x80x9cA 85 Volt High Performance Silicon Complementary Bipolar Technology for High Voltage Analog Applicationsxe2x80x9d, Proceedings of the 24th European Solid State Device Research Conference, 1994, p. 217, discusses a high performance complementary bipolar technology for use in fabricating high-frequency and high-voltage analog circuits. The technology described uses an N-type epitaxial silicon layer to form the collector for the NPN device. A sinker-up region for minimizing collector resistance of the NPN device is implanted prior to growth of the epitaxial layer. Sinker-down regions are used for both the NPN and PNP devices. The breakdown voltage of the devices is less than 100 volts, which is insufficient for some high voltage applications. In addition, the process cannot be scaled because junction isolation is used. Another disadvantage is that the breakdown voltage of the NPN transistor cannot be optimized independently of the PNP transistor, leading to a compromising of the performance of the NPN transistor.
The article entitled xe2x80x9cNovel Scaling Technique for High Voltage Analog ICsxe2x80x9d, Solid State Technology, March, 1991, page 85, describes how a 15 to 40 percent scaling of high voltage analog devices was obtained by replacing a single epitaxial layer with three, graded layers having different thicknesses and resistivities. This reduced the thermal cycles required for junction isolation and the lateral out-diffusion of dopants which increase the width of the isolation region. However, a disadvantage of this process is that it cannot be used to produce truly complementary bipolar devices because the NPN collector doping differs from the PNP collector doping. The article entitled xe2x80x9cNovel IC Structure for 150V High-Voltage Consumer ICxe2x80x9d, IEEE Transactions on Consumer Electronics, vol. CE-26, August, 1980, p. 367, describes how a single epitaxial layer having a varying thickness is used to form both high-voltage and small signal devices on the same substrate. The isolation region between the two devices is diffused in the thin region of the epitaxial layer and the high voltage device is formed in a well in the thick region of the epitaxial layer. The process requires that complex processing steps be used to planarize the substrate and to adjust the thicknesses of the epitaxial layer in the two regions.
U.S. Pat. No. 4,089,021, issued May 9, 1978, discloses a method of fabricating a high-voltage semiconductor device in which the lateral extent of the isolation regions can be reduced to provide increased integration density of the devices. This is accomplished by forming one or more recessed regions in a substrate and then growing an epitaxial layer over the substrate. As with the IEEE article discussed above, by planarizing the epitaxial layer, isolation regions may be formed in a thinner region of the layer while the high voltage device may be formed in the thicker regions.
U.S. Pat. No. 5,065,213, issued Nov. 12, 1991, and U.S. Pat. No. 5,118,635, issued Jun. 2, 1992, both naming Frisina et al. as inventors, disclose a process for manufacturing a high voltage bipolar power transistor and low voltage MOS power transistor on a common substrate. The process uses two epitaxial layers with a vertical NPN transistor formed in the first layer and a CMOS transistor formed on top of the NPN device""s emitter in the second layer. The epitaxial layers have different characteristics since they are used to form different types of devices. However, the fabrication process described in the ""231 and ""635 patents does not use sinker regions to reduce the collector contact resistance and is not compatible with complementary bipolar process flows.
U.S. Pat. No. 4,780,430, issued Oct. 25, 1988, naming Musumeci et al. as inventors, discloses a process for fabricating a high voltage monolithic semiconductor device that contains a power transistor and an integrated control circuit. In the process, three epitaxial layers are grown with two of the layers having different thicknesses and the same Nxe2x88x92 doping concentration, and the third layer being doped N type. A N+ type substrate is used and the devices are not isolated. The process described in the ""430 patent does not use sinker regions to reduce the collector contact resistance and is not compatible with the fabrication of complementary bipolar devices.
What is desired is a method of fabricating high voltage vertical NPN and PNP devices on a common substrate, where the devices are truly complementary (have the same structure) and can have their parameters optimized independently of each other. It is further desired that the collector contact resistance of the devices be minimized by the use of deep sinker and buried layer structures to improve the performance of the devices. It is also desired that the fabrication method be compatible with trench isolation techniques to permit scaling of the process. This requires that the trench depth be minimized. Finally, it is desired that the high voltage device process be compatible with the formation of lower voltage vertical NPN and PNP devices, and that the lower voltage devices be formed without the use of additional masking steps and be capable of being optimized independently of the high voltage devices.
The present invention is directed to a method of making high voltage complementary bipolar and BiCMOS devices on a common substrate. The bipolar devices are vertical NPN and PNP transistors having the same structure. The fabrication process utilizes trench isolation and thus is scalable. The process uses two epitaxial silicon layers to form the high voltage NPN collector, with the PNP collector formed from a p-well diffused into the two epitaxial layers. The collector contact resistance is minimized by the use of sinker up/down structures formed at the interface of the two epitaxial layers. The process minimizes the thermal budget and therefore the up diffusion of the NPN and PNP buried layers. This maximizes the breakdown voltage at the collector-emitter junction for a given epitaxial thickness. The epitaxial layers may be doped as required depending upon the specifications for the high voltage NPN device. The process is compatible with the fabrication of low voltage devices, which can be formed by placing the sinker regions under the emitter region. The thicknesses of the two epitaxial layers may be adjusted as required depending upon the specifications for the low voltage devices.
The high voltage complementary bipolar and BiCMOS process is based on a silicon-on-insulator structure which forms the substrate for fabrication of the devices. Buried layers for the NPN and PNP devices are formed by well known masking, implanting and anneal steps. A first epitaxial layer is then grown over the surface of the substrate. A thin screen oxide layer is then grown over the epitaxial layer. N+ and P+ type sinker up and/or sinker down regions are then formed in the first epitaxial layer. The sinker regions are used both as part of a low resistance contact for the high voltage device collectors and as a buried layer for the low voltage devices being fabricated on the same substrate. The structure is annealed and cleaned and then a second epitaxial layer is grown over the surface of the substrate.
Again, a thin screen oxide layer is grown and N+ and P+ type sinker up and/or sinker down regions are formed in the second layer. A pad or screen oxide layer is then grown over the top surface of the substrate. Optional N+ and P+ type sinker down structures may then be formed. A p-well structure is then formed in the PNP device regions. Nitride layer deposition and field oxide layer formation is then performed. Trench isolation structures are then formed in the substrate between each of the active device regions. Diffusion of the sinker and p-well regions is then performed. Finally, the processing steps needed to complete formation of the CMOS, vertical high voltage NPN and PNP, and vertical low voltage NPN and PNP devices are performed on the active device regions.
Further objects and advantages of the present invention will become apparent from the following detailed description and accompanying drawings.